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參數(shù)資料
| 型號： | ICS9148F-14LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 807K |
| 代理商： | ICS9148F-14LF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-14
Block Diagram
Pentium/ProTM Clock Chip for Mobile/Docking Systems
9148-14 Rev B 02/20/98
Pentium is a trademark of Intel Corporation.
Generates system clocks for CPU,AGP, SDRAM, PCI,
plus 14.314 MHz REF(0:3), USB, or Super I/O
Skew defined for Mobile/Docking Station use
I2C serial configuration interface provides output clock
disabling and other functions
MODE input pin selects optional power management
input control pins
Fixed output separately selectable as 24 or 48MHz
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU
3.3Voutputs: SDRAM, PCI, REF, 48/24 MHz,AGP
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48pin300milSSOP
I2C pins 5V input tolerant
The ICS9148-14 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Mobile/Docking systems that will
provide all necessary clock timing.
Features include three CPU, oneAGP, early PCI, five PCI and
eight SDRAM clocks. Four reference outputs are available
equal to the crystal frequency. The single AGP output is
defined as 2X the PCI BUS speed. For Mobile Docking station
the Early PCI is 1.5ns ±250ps leading the PCI (0:4). SDRAM
leads CPU by 1.2ns ±250ps. CPU to PCI (0:4) skew is 500ps
max.
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:2) clocks, PCI_STOP# will stop
E_PCICLK, PCICLK (0:4) andAGPclocks. Both low will also
stop SDRAM outputs. CPU output buffer strength is controlled
by the CPU 3.3_2.5# pin to match VDDL voltage.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. SDRAM outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining50±5% duty cycle. The REF clock outputs typically
providebetterthan0.5V/nsslewrates,REF0into47pF,REF(1:3)
into 20pF loads. PCI outputs are sized for EMI imporvement,
providing 0.5v/ns slew rate into 20pF.
The ICS9148-14 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Functionality
VDD(1:4)3.3V±5%,VDDL1,22.5±5%or3.3±5%0-70°C
Crystal (X1, X2) = 14.31818 MHz
Pin Configuration
48-Pin SSOP
SEL
CPUCLK, SDRAM
(MHz)
PCICLK
(MHz)
AGP
(MHz)
0
Reserved
-
1
66.6
33.3
66.6
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9148F-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| ICS9148F-18 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F-20 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| ICS9148F-25 | 功能描述:IC CLK SYNTHESIZER CHIP 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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