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參數資料
| 型號： | ICS9148F-17-LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數： | 1/16頁 |
| 文件大?。?/td> | 473K |
| 代理商： | ICS9148F-17-LF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-17
Block Diagram
Pentium is a trademark of Intel Corporation
I
2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
9148-17 Rev F 10/21/99
Pin Configuration
3.3Voutputs: SDRAM,AGP, PCI, REF, 48/24 MHz
2.5V or 3.3V outputs: CPU
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
CPU to PCI skew = 2 to 6ns
No external load cap for CL=18pF crystals
250 ps max CPU, PCI clock skew
Smooth CPU frequency transition among all CPU
frequencies.
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs.
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4=AGP(0:1)
VDDL=CPUCLK(0:3)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
The ICS9148-17 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Features include four CPU, six PCI, two AGP (=2xPCI) and
Twelve SDRAM clocks. Two reference outputs are available
equal to the crystal frequency. One 48 MHz for USB, and one
24 MHz clock for Super IO. Built in ±1.5%, 0.6% center or down
spread spectrum modulation to reduce EMI. Serial
programming I2C interface allows changing functions, stop
clock programing and frequency selection. Additionally, the
device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates.
CPU_STOP#
PCI_STOP#
PLL2
PLL1
Spread
Spectrum
48MHz
24MHz
REF (0:1)
CPUCLK (0:3)
SDRAM (0:11)
PCICLK (0:4)
PCICLK_F
X1
X2
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
SDATA
SCLK
FS(0:2)
MODE
CPU3.3#_2.5
Control
Logic
Config.
Reg.
AGP(0:1)
LATCH
POR
PCI_STOP
CPU_STOP
2
4
12
5
3
/2
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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PDF描述 |
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| ICS9148F-17 | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-18LF | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9148F-25 | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS9148F-18 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F-20 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| ICS9148F-25 | 功能描述:IC CLK SYNTHESIZER CHIP 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| ICS9148F-25T | 功能描述:IC CLK SYNTHESIZER CHIP 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
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