參數(shù)資料
型號(hào): ICS9148F-03
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, SSOP-48
文件頁(yè)數(shù): 1/12頁(yè)
文件大小: 539K
代理商: ICS9148F-03
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-03
Block Diagram
Pentium is a trademark of Intel Corporation
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
9148-03RevA091997P
Pin Configuration
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), XTAL, 24MHz, 48MHz
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPU (0:3)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
** Internal Pulldown to GND
3.3V outputs: SDRAM, PCI, REF, 48/24MHz.
2.5V or 3.3V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns,
center 2.6 ns.
No external load cap for CL=18pF crystal
±250 ps CPU, PCI clock skew
400ps (cycle to cycle) CPU jitter
2ms power up clock stable time.
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant input.
The ICS9148-03 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
Features include four CPU, seven PCI and Twelve SDRAM
clocks. Two reference outputs are available equal to the
crystal frequency. Plus the IOAPIC output powered by
VDDL1. One 48 MHz for USB, and one 24 MHz clock for
Super IO. Spread Spectrum built in - ±1.5% modulation to
reduce the EMI. Rise time adjustment for VDD at 3.3V or
2.5V CPU. Additionally, the device meets the Pentium
power-up stabilization, which requires that CPU and PCI
clocks be stable within 2ms after power-up. It is not
recommended to use I/O dual function pin for the slots
(ISA, PCI, CPU, DIMM). The add on card might have a pull up
or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK
outputs typically provide better than 1V/ns slew rate into
20pF loads while maintaining 50±5% duty cycle. The REF
and 24 and 48 MHz clock outputs typically provide better
than 0.5V/ns slew rates.
ADVANCE INFORMATION documents contain information on
new products in the sampling or preproduction phase of devel-
opment. Characteristic data and other specifications are subject to
change without notice.
相關(guān)PDF資料
PDF描述
ICS9148F-08 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-11 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-14LF 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-14 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-14LF 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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