- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67703 > ICS87973DYI-147T (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS87973DYI-147T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | ICS87973DYI-147T |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
87973DYI-147
www.icst.com/products/hiperclocks.html
REV. A AUGUST 26, 2003
10
Integrated
Circuit
Systems, Inc.
ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
FRZ
Latched
FRZ
C
lo
cke
d
Qx FREEZE Internal
Qx Internal
Qx Out
FRZ_CLK
FRZ_DATA
Star
t
Bit
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3 QSYNC
APPLICATION INFORMATION
FIGURE 2A. FREEZE DATA INPUT PROTOCOL
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output of
ICS87973I-147 (Except QC0 and QFB) can be individually fro-
zen (stopped in the logic “0” state) using a simple serial inter-
face to a 12 bit shift register. A serial interface was chosen to
eliminate the need for each output to have its own Output En-
able pin, which would dramatically increase pin count and pack-
age cost. Common sources in a system that can be used to
drive the ICS87973I-147 serial interface are FPGA’s and ASICs.
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which
can be frozen has its own freeze enable bit in the 12 bit shift
register. The sequence is started by supplying a logic “0” start
bit followed by 12NRZ freeze enable bits. The period of each
FRZ_DATA bit equals the period of the FRZ_CLK signal. The
FRZ_DATA serial transmission should be timed so the
ICS87973I-147 can sample each FRZ_DATA bit with the rising
edge of the FRZ_CLK signal. To place an output in the freeze
state, a logic “0” must be written to the respective freeze enable
bit in the shift register. To unfreeze an output, a logic “1” must be
written to the respective freeze enable bit. Outputs will not be-
come enabled/disabled until all 12 data bits are shifted into the
shift register. When all 12 data bits are shifted in the register, the
next rising edge of FRZ_CLK will enable or disable the outputs.
If the bit that is following the 12th bit in the register is a logic “0”,
it is used for the start bit of the next cycle; otherwise, the device
will wait and won’t start the next cycle until it sees a logic “0” bit.
Freezing and unfreezing of the output clock is synchronous (see
the timing diagram below). When going into a frozen state, the
output clock will go LOW at the time it would normally go LOW,
and the freeze logic will keep the output low until unfrozen. Like-
wise, when coming out of the frozen state, the output will go
HIGH only when it would normally go HIGH. This logic, there-
fore, prevents runt pulses when going into and out of the frozen
state.
FIGURE 2B. OUTPUT DISABLE TIMING
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS87973DYI-147LFT | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| ICS87973DYI-147LFT | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| ICS87973DYIT | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| ICS87974AY-01LF | PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| ICS87974AYI-01 | PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS87973DYILF | 功能描述:IC CLK MULT/ZD BUFFER 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS87973DYILFT | 功能描述:IC CLK MULT/ZD BUFFER 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS87974CYILF | 功能描述:IC CLK GEN LVCMOS/LVTTL 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS87974CYILFT | 功能描述:IC CLOCK GEN 1-15 PLL 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS879893AYILF | 功能描述:IC CLK GEN LVCMOS/LVTTL 48-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。