參數(shù)資料
型號(hào): ICS87949AYI-147
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 87949 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封裝: 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
文件頁(yè)數(shù): 1/12頁(yè)
文件大?。?/td> 287K
代理商: ICS87949AYI-147
87949AYI-147
www.icst.com/products/hiperclocks.html
REV. C JUNE 13, 2005
1
Integrated
Circuit
Systems, Inc.
ICS87949I-147
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87949I-147 is a low skew, ÷1, ÷2
LVCMOS/LVTTL Clock Generator and a member
of the HiPerClockS family of High Performance
Clock Solutions from ICS. The ICS87949I-147
has selectable single ended clock or LVPECL
clock inputs. The single ended clock input accepts LVCMOS
or LVTTL input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50
Ω series or
parallel terminated transmission lines. The effective fanout can
be increased from 15 to 30 by utilizing the ability of the out-
puts to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87949I-147 is characterized at 3.3V and 2.5V. Guaran-
teed output and part-to-part skew characteristics make the
ICS87949I-147 ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
15 single ended LVCMOS/LVTTL outputs,
7
Ω typical output impedance
Selectable LVCMOS/LVTTL or LVPECL clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum input frequency: 250MHz
Output skew: 250ps (maximum)
Part-to-part skew: 1.0ns (maximum)
Bank skew: 65ps (maximum)
3.3V or 2.5V supply voltage
-40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y Package
Top View
HiPerClockS
ICS
nc
V
DDD
QD4
GND
QD3
V
DDD
QD2
GND
QD1
V
DDD
QD0
GND
nc
MR/nOE
CLK_SEL
VDD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
39
38
37
36
35
34
33
32
31
30
29
28
27
52 51 50 49 48 47 46 45 44 43 42 41 40
nc
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
GND
QD5
nc
V
DDB
QB2
GND
QB1
V
DDB
QB0
GND
QA1
V
DDA
QA0
GND
ICS87949I-147
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
MR/nOE
QA0:QA1
QB0:QB2
QC0:QC3
QD0:QD5
CLK_SEL
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
0
1
÷1
÷2
0
1
0
1
0
1
0
1
R
0
1
相關(guān)PDF資料
PDF描述
ICS87949AYILF 87949 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
ICS87949AYILFT 87949 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
ICS87949AYT LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
ICS87950AYLF-T 180 MHz, OTHER CLOCK GENERATOR, PQFP32
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