參數(shù)資料
型號(hào): ICS87949AYI-01
元件分類: 時(shí)鐘及定時(shí)
英文描述: LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
文件頁數(shù): 1/13頁
文件大小: 274K
代理商: ICS87949AYI-01
87949AYI-01
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 1, 2003
1
Integrated
Circuit
Systems, Inc.
ICS87949I-01
LOW SKEW
÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87949I-01 is a low skew, ÷1, ÷2 Clock
Generator and a member of the HiPerClockS
family of High Performance Clock Solutions from
ICS. The ICS87949I-01 has selectable single
ended clock or LVPECL clock inputs. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The low impedance LVCMOS/LVTTL outputs are
designed to drive 50
series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 15 to
30 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87949I-01 is characterized at 3.3V core/3.3V output
and 3.3V core/2.5V output. Guaranteed bank, output and part-
to-part skew characteristics make the ICS87949I-01 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
FEATURES
15 single ended LVCMOS/LVTTL outputs,
7
typical output impedance
Selectable LVCMOS/LVTTL or LVPECL clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum input frequency: 250MHz
Output skew: 250ps (maximum)
Part-to-part skew: 1ns (maximum)
Full 3.3V or mixed 3.3V core/2.5V output supply
-40°C to 85°C ambient operating temperature
Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
BLOCK DIAGRAM
PIN ASSIGNMENT
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
HiPerClockS
ICS
V
DDD
QD4
GND
QD3
V
DDD
QD2
GND
QD1
V
DDD
QD0
GND
MR/nOE
CLK_SEL
VDD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
nc
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
GND
QD5
V
DDB
QB2
GND
QB1
V
DDB
QB0
GND
QA1
V
DDA
QA0
GND
ICS87949I-01
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
MR/nOE
QA0, QA1
QB0:QB2
QC0:QC3
QD0:QD5
CLK_SEL
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
0
1
÷1
÷2
0
1
0
1
0
1
0
1
R
0
1
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PDF描述
ICS87949AYI-01 LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
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