參數(shù)資料
型號(hào): ICS87946AYI-01LF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件頁(yè)數(shù): 15/15頁(yè)
文件大?。?/td> 1230K
代理商: ICS87946AYI-01LF
ICS87946I-01
LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT / ICS 16:1, SINGLE-ENDED MULTIPLEXER
9
ICS87946AYI-01 REV. BMAY 4, 2007
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
OUTPUTS:
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 1. Single-Ended Signal Driving Differential Input
Single Ended Clock Input
VDD
PCLK
nPCLK
R1
C1
0.1u
R2
1K
V_REF
相關(guān)PDF資料
PDF描述
ICS87946AYI-01T LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS87949AY-01LF LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
ICS87949AY-01 LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
ICS87949AY-01LFT LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
ICS87949AY-01T LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
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