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參數(shù)資料
| 型號： | ICS8745BYIT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 1383K |
| 代理商： | ICS8745BYIT |
ICS8745BI
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT / ICS LVDS ZERO DELAY CLOCK GENERATOR
14
ICS8745BYIREV. C APRIL 16, 2007
The following component footprints are used in this layout
example.
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on the
component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VDDA pin as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the same
length.
Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces.
Placement of vias on the traces can affect the trace
characteristic impedance and hence degrade signal
integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
Figure 5B. PCB Board Layout for ICS8745BI
C16
GND
U1
C5
50 Ohm
Traces
C2
VDDA
VDDO
VIA
Pin 1
C4
R7
C11
VDD
C6
C1
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| ICS8745BYI | 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS874S02AMILF | 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS874S02AMI | 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS874S02AMIT | 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS874S02BMILF | 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
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