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參數(shù)資料
| 型號： | ICS8745BYIT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 1383K |
| 代理商： | ICS8745BYIT |
ICS8745BI
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT / ICS LVDS ZERO DELAY CLOCK GENERATOR
10
ICS8745BYIREV. C APRIL 16, 2007
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS8745BI provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDDA and VDDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10
resistor along with a 10F and a .01F
bypass capacitor should be connected to each VDDA pin. The 10
resistor can also be replaced by a ferrite bead.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
VDD
VDDA
3.3V
10
10F
.01F
V_REF
Single Ended Clock Input
VDD
CLKx
nCLKx
R1
1K
C1
0.1u
R2
1K
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