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參數(shù)資料
| 型號(hào)： | ICS8745BMI-21LF |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, MO-119, SOIC-20 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大小： | 207K |
| 代理商： | ICS8745BMI-21LF |
8745BMI-21
www.icst.com/products/hiperclocks.html
REV. B MARCH 17, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8745BI-21
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 2. In a 100
differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100
across near the receiver in-
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
100 Ohm Differiential Transmission Line
R1
100
3.3V
+
-
LVDS_Driv er
3.3V
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
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