參數(shù)資料
型號(hào)： ICS8745BMI-21LF
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝： 7.50 X 12.80 MM, 2.30 MM HEIGHT, MO-119, SOIC-20
文件頁(yè)數(shù)： 1/15頁(yè)
文件大?。?/td> 207K
代理商： ICS8745BMI-21LF
8745BMI-21
www.icst.com/products/hiperclocks.html
REV. B MARCH 17, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8745BI-21
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8745BI-21 is a highly versatile 1:1 LVDS
Clock Generator and a member of the
HiPerClockSfamily of High Performance Clock
Solutions from ICS. The ICS8745BI-21 has a fully
integrated PLL and can be configured as zero
delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 700MHz. The Reference Divider, Feed-
back Divider and Output Divider are each programmable,
thereby allowing for the following output-to-input frequency
ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback
allows the device to achieve “zero delay” between the input
clock and the output clock. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
FEATURES
1 differential LVDS output pair designed to meet
or exceed the requirements of ANSI TIA/EIA-644,
1 differential feedback output pair
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 30ps (maximum)
Output skew: 40ps (maximum)
Static phase offset: 25ps ± 125ps
3.3V supply voltage
-40°C to 85°C ambient operating temperature
HiPerClockS
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS8745BI-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
GND
Q
nQ
VDDO
PLL_SEL
CLK
nCLK
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q
nQ
QFB
nQFB
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
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