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參數(shù)資料
| 型號： | ICS8745BM-21LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8745 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ICS8745BM-21LF |
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT / ICS LVDS ZERO DELAY CLOCK GENERATOR
15
ICS8745BM-21REV. C APRIL 17, 2007
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8745B-21.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8745B-21 is the sum of the core power plus the analog power plus the power dissipated in the
load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (125mA + 17mA) = 492mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 59mA = 204mW
Total Power_MAX = 492mW + 204mW = 696mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.696W * 39.7°C/W = 97.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Linear Feet per Minute
0200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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