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參數(shù)資料
| 型號： | ICS870S208BKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 870S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封裝： | 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, VFQFN-32 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 943K |
| 代理商： | ICS870S208BKLF |
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/
DIVIDER AND GLITCHLESS SWITCH
ICS870S208
IDT / ICS LVCMOS FANOUT BUFFER W/DIVIDER
1
ICS870S208
BK REV. A NOVEMBER 9, 2007
PRELIMINARY
GENERAL DESCRIPTION
The ICS870S208 is a low skew, 8 output LVCMOS /
LVTTL Fanout Buffer with selectable divider and a
member of the HiPerClockS family of High
Perfor mance Clock Solutions from IDT. The
ICS870S208 has 2 selectable inputs that accept a
variety of differential input types. The device provides the cap-
ability to suppress any glitch at the outputs of the device during
an input clock switch to enhance clock redundancy in fault tole-
rant applications. The low impedance LVCMOS outputs are
designed to drive 50
Ω series or parallel terminated transmission
lines. The effective fanout can be increased from 8 to 16 by utilizing
the ability of the outputs to drive two series terminated lines. The
divide select inputs, DIV_SELA and DIV_SELB, control the output
frequency of each bank. The output banks can be independently
selected for ÷1 or ÷2 operation. The output enable pins assigned
to each output, support enabling and disabling of each output
individually.
The ICS870S208 is characterized at full 3.3V and 2.5V, and mixed
3.3V/2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS870S208 ideal for
high performance, single ended applications.
FEATURES
Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)
Each output has individual synchronous output enable
Two selectable differential CLKx/nCLKx clock inputs
Dual differential input pairs can accept the following differen-
tial input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 250MHz
Independent bank control for
÷1 or ÷2 operation
Glitchless output behavior during input switch
Output skew: 50ps (typical) @ 3.3V
Bank skew: 30ps (typical) @ 3.3V
Supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
HiPerClockS
ICS
ICS870S208
32-Lead VFQFN
5mm x 5mm x 0.9
25mm
package body
K Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OE_B3
OE_B2
OE_B1
OE_B0
OE_A3
OE_A2
OE_A1
OE_A0
DIV_SELB
CLK0
nCLK0
VDD
CLK_SEL
CLK1
nCLK1
DIV_SELA
GND
QB1
QB0
V
DDOB
V
DDO
A
QA1
QA0
GND
QB3
QB2
V
DDOB
V
DDO
A
QA3
QA2
GND
÷1
÷2
0
1
0
1
0
1
Pulldown
Pullup
Pulldown
QA0
DIV_SELA
CLK0
nCLK0
CLK1
CLK_SEL
nCLK1
DIV_SELB
OE_A0
QA1
OE_A1
QA2
OE_A2
QA3
OE_A3
QB0
OE_B0
QB1
OE_B1
QB2
OE_B2
QB3
OE_B3
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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