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| 型號(hào)： | ICS871004AGI-04LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 871004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大小： | 643K |
| 代理商： | ICS871004AGI-04LFT |
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DIFFERENTIAL-TO-0.7V DIFFERENTIAL
PCI EXPRESS JITTER ATTENUATOR
ICS871004I-04
IDT / ICS 0.7V DIFFERENTIAL JITTER ATTUNUATOR
1
ICS871004AGI-04 REV A JANUARY 17, 2008
PRELIMINARY
GENERAL DESCRIPTION
The ICS871004I-04 is a high perfor mance
Differential-to-0.7V Differential Jitter Attenuator
designed for use in PCI Express systems. In some
PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are
generated from a low bandwidth, highphase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may
be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer and
from the system board. The ICS871004I-04 has 3 PLL
bandwidth modes: 200kHz, 400kHz and 800kHz. The 200kHz
mode will provide maximum jitter attenuation, but with higher
PLL tracking skew and spread spectrum modulation from the
motherboard synthesizer may be attenuated. The 400kHz
provides an intermediate bandwidth that can easily track tri-
angular spread profiles, while providing good jitter attenuation.
The 800kHz bandwidth provides the best tracking skew and
will pass most spread profiles, but the jitter attenuation will not
be as good as the lower bandwidth modes. The ICS871004I-
04 can be set for different modes using the F_SEL pins as
shown in Table 3C.
The ICS871004I-04 uses IDT’s 3rd Generation FemtoClockTM PLL
technology to achieve the lowest possible phase noise. The device
is packaged in a 24 Lead TSSOP package, making it ideal for
use in space constrained applications such as PCI Express add-
in cards.
Features
Four 0.7V differential output pairs
One differential clock input
CLK and nCLK supports the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 640MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 19ps (typical)
Additive phase jitter, RMS: 0.23ps (typical)
3.3V operating supply
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
HiPerClockS
ICS
Q0
nQ0
BLOCK DIAGRAM
BW_SEL[1:0]
0 0 = PLL Bandwidth: ~200kHz
0 1 = PLL Bandwidth: ~400kHz (default)
1 0 = PLL Bandwidth: ~800kHz
1 1 = PLL BYPASS
PLL BANDWIDTH
0 0 ÷5
(default)
0 1 ÷4
1 0 ÷2
1 1 ÷1
÷5
VCO
490 - 640MHz
Phase
Detector
2
-
+
M
U
X
Control
Logic
Pulldown
OE
F_SEL[1:0]
BW_SEL[1:0]
CLK
nCLK
MR
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pulldown
Pullup
PIN ASSIGNMENT
ICS871004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ0
nQ2
Q2
VDD
IREF
GND
MR
BW_SEL0
VDDA
F_SEL0
VDD
OE
1
2
3
4
5
6
7
8
9
10
11
12
Q0
VDD
Q1
nQ1
Q3
nQ3
BW_SEL1
F_SEL1
GND
nCLK
CLK
24
23
22
21
20
19
18
17
16
15
14
13
IREF
Pulldown:Pullup
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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