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參數(shù)資料
| 型號： | ICS8702BYLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8702 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 438K |
| 代理商： | ICS8702BYLF |
Integrated
Circuit
Systems, Inc.
8702BY
www.icst.com/products/hiperclocks.com
REV. D JANUARY 17, 2006
1
ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8702 is a low skew,
÷1, ÷2 Differential-to-
LVCMOS Clock Generator and a member of the
HiPerClockSfamily of High Performance Clock
Solutions from ICS. The ICS8702 is designed to
translate any differential signal levels to
LVCMOS/LVTTL levels. True or inverting, single-ended to
LVCMOS translation can be achieved with a resistor bias
on the nCLK or CLK inputs, respectively. The effective fan-
out can be increased from 20 to 40 by utilizing the ability of
the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1, ÷2
or a combination of ÷1 and ÷2 modes. The bank enable in-
puts, BANK_EN0:1, supports enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
enabling and disabling of all outputs simultaneously.
The ICS8702 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output, multiple frequency and part-to-part skew char-
acteristics make the ICS8702 ideal for those clock dis-
tribution applications demanding well defined performance
and repeatability.
FEATURES
Twen
ty LVCMOS outputs, 7
Ω typical output impedance
One differential clock input pair
CLK, nCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 250MHz
Translates any differential input signal (LVPECL, LVHSTL,
LVDS) to LVCMOS levels without external bias networks
Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
Bank enable logic allows unused banks to be disabled in
reduced fanout applications
Output skew: 200ps (maximum)
Bank skew: 150ps (maximum)
Part-to-part skew: 650ps (maximum)
Multiple frequency skew: 250ps (maximum)
3.3V or mixed 3.3V input, 2.5V output operating
0°C to 70°C ambient operating temperature
Other divide values available on request
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
DIV_SELA
DIV_SELB
CLK
nCLK
V
DD
BANK_EN0
GND
BANK_EN1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8702
HiPerClockS
ICS
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QA0:QA4
QB0:QB4
QC0:QC4
QD0:QD4
CLK
nCLK
Bank Enable
Logic
÷1
÷2
1
0
1
0
1
0
1
0
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