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參數(shù)資料
| 型號： | ICS8701-01AYLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 76K |
| 代理商： | ICS8701-01AYLF-T |
Integrated
Circuit
Systems, Inc.
8701AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 29, 2001
ICS8701-01
LOW SKEW
÷1, ÷2
CLOCK GENERATOR W/POLARITY CONTROL
1
GENERAL DESCRIPTION
The ICS8701-01 is a low skew,
÷1, ÷2 Clock
Generator and a member of the HiPerClockS
family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS outputs
are designed to drive 50
series or parallel termi-
nated transmission lines. The effective fanout can be increased
from 20 to 40 by utilizing the ability of the outputs to drive two
series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset/output en-
able input, nMR/OE, resets the internal dividers and controls
the active and high impedance states of all outputs. The output
polarity inputs, INV0:1, control the polarity (inverting or non-
inverting) of the outputs of each bank. Outputs QA0-QA4 are
inverting for every combination of the INV0:1 input. The timing
relationship between the inverting and non-inverting outputs at
different frequencies is shown in the Timing Diagrams.
The ICS8701-01 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701-01 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
FEATURES
20 LVCMOS outputs, 7
typical output impedance
1 LVCMOS clock input
Maximum output frequency up to 250 MHz
Selectable inverting and non-inverting outputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
Output skew: 300ps (maximum)
Part-to-part skew: 700ps (maximum)
Bank skew: 250ps (maximum)
Multiple frequency skew: 350ps (maximum)
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
HiPerClockS
,&6
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
INV0
INV1
QA0 - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
CLK
1
0
÷1
÷2
1
0
1
0
1
0
Output
Polarity
Control
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
VDDOC
QC4
QD0
VDDOD
QD1
GND
QD2
GND
QD3
VDDOD
QD4
QB1
VDDOB
QB0
QA4
VDDOA
QA3
GND
QA2
GND
QA1
VDDOA
QA0
DIV_SELA
DIV_SELB
CLK
GND
V
DD
INV0
GND
INV1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDOB
QB4
QC0
V
DDOC
QC1
GND
QC2
GND
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8701-01
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