參數(shù)資料
型號: ICS87016AYI
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
文件頁數(shù): 1/13頁
文件大?。?/td> 156K
代理商: ICS87016AYI
Integrated
Circuit
Systems, Inc.
87016AYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 13, 2003
1
ICS87016I
LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87016I is a low skew, 1:16 LVCMOS/LVTTL
Clock Generator and is a member of the
HiPerClockS family of High Performance Clock
Solutions. The device has 4 banks of 4 outputs
and each bank can be independently selected for
÷1 or ÷2 frequency operation. Each bank also has its own power
supply pins so that the banks can operate at the following dif-
ferent voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50
series or
parallel terminated transmission lines.
The divide select inputs, DIV_SELA:DIV_SELD, control the
output frequency of each bank. The output banks can be
independently selected for
÷1 or ÷2 operation. The bank enable
inputs, CLK_ENA:CLK_END, support enabling and disabling
each bank of outputs individually. The CLK_ENA:CLK_END
circuitry has a synchronizer to prevent runt pulses when
enabling or disabling the clock outputs. The master reset
input, nMR/OE, resets the
÷1/÷2 flip flops and also controls the
active and high impedance states of all outputs. This pin has
an internal pull-up resistor and is normally used only for test
purposes or in systems which use low power modes.
The ICS87016I is characterized to operate with the core at 3.3V
and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output,
and part-to-part skew characteristics make the 87016I ideal for
those clock applications demanding well-defined performance
and repeatability.
FEATURES
16 LVCMOS/LVTTL outputs (4 banks of 4 outputs)
Selectable differential CLK1, nCLK1 or LVCMOS clock input
CLK1, nCLK1 pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK0 supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Independent bank control for
÷1 or ÷2 operation
Independent output bank voltage settings for 3.3V, 2.5V,
or 1.8V operation
Asynchronous clock enable/disable
Output skew: 170ps (maximum)
Bank skew: 50ps (maximum)
Part-to-part skew: 800ps (maximum)
3.3V core, 3.3V, 2.5V, or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
HiPerClockS
,&6
48-Pin LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
GND
QC2
V
DDOC
QC3
GND
QD0
V
DDOD
QD1
GND
QD2
V
DDOD
QD3
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
VDD
CLK0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
nMR/OE
GND
QB0
VDDOB
QB1
GND
QB2
VDDOB
QB3
GND
QC0
VDDOC
QC1
QA3
V
DDOA
QA2
GND
QA1
V
DDOA
QA0
GND
CLK_SEL
nCLK1
CLK1
V
DD
ICS87016I
nMR/OE
CLK0
CLK1
nCLK1
CLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
QA0:QA3
QB0:QB3
QC0:QC3
QD0:QD3
0
1
0
1
0
1
0
1
0
÷1
÷2
4
LE
D
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