- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67698 > ICS853S202AYI (INTEGRATED DEVICE TECHNOLOGY INC) 853S SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 PDF資料下載
參數(shù)資料
| 型號： | ICS853S202AYI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 853S SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 559K |
| 代理商： | ICS853S202AYI |
IDT / ICS 3.3V, 2.5V LVPECL MULTIPLEXER
11
ICS853S202AKI REV. A JANUARY 25, 2007
ICS853S202I
12:2, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL MULTIPLEXER
PRELIMINARY
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
INPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
Ω resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
相關PDF資料 |
PDF描述 |
|---|---|
| ICS854054AGLF | 854054 SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO16 |
| ICS854054AGT | 854054 SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO16 |
| ICS854054AG | 854054 SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO16 |
| ICS854054AG | 854054 SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO16 |
| ICS854057AGLFT | 854057 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS853S310AVILF | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS853S314AFILF | 功能描述:IC CLOCK BUFFER MUX 2:4 20-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:HiPerClockS™ 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:管件 |
| ICS853S314AFILFT | 功能描述:IC CLOCK BUFFER MUX 2:4 20-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:HiPerClockS™ 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:管件 |
| ICS853S314AGILF | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:HiPerClockS™ 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:管件 |
| ICS853S314AGILFT | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:HiPerClockS™ 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。