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參數資料
| 型號： | ICS8537AYT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件頁數： | 2/13頁 |
| 文件大?。?/td> | 140K |
| 代理商： | ICS8537AYT |
8537AY
www.icst.com/products/hiperclocks.html
REV. A MAY 29, 2002
10
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8537
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVPECL CLOCK BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
FIGURE 1 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC - 2V
F
IN
F
OUT
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 2B - LVPECL OUTPUT TERMINATION
FIGURE 2A - LVPECL OUTPUT TERMINATION
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