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參數(shù)資料
| 型號(hào)： | ICS84330BYLNT |
| 英文描述： | 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | 700MHz的，低抖動(dòng)，晶體至3.3V的差分LVPECL頻率合成器 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 368K |
| 代理商： | ICS84330BYLNT |
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
11
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
6B. PCB B
OARD
L
AYOUT
FOR
ICS84330
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C3 and C4, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and
U1 should be kept to a minimum to avoid unwanted parasitic in-
ductance and capacitance. Other signal traces should not be
routed near the crystal traces.
R7
Signals
Traces
VCCA
C1
C4
VCC
50 Ohm
Traces
C11
C3
GND
PIN 2
C2
PIN 1
C16
U1
X1
VIA
VCCA
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| ICS8442AYLFT | 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER |
| ICS8442AYT | 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS84330BYT | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330C | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330CI | 制造商:ICS 制造商全稱:ICS 功能描述:720MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330CM-01 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330CM-01LF | 功能描述:IC FREQ SYNTHESIZER 28SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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