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參數(shù)資料
| 型號(hào)： | ICS8431CM-11T |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 255 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 7.50 X 18.05, 2.25 MM HEIGHT, SOIC-28 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 2136K |
| 代理商： | ICS8431CM-11T |
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8431CM-11
www.icst.com/products/hiperclocks.html
REV. B AUGUST 7, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, CRYSTAL OSCILLATOR-
TO
-3.3V LVPECL FREQUENCY SYNTHESIZER
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 4B - LVPECL OUTPUT TERMINATION
3.3V
FOUT
FIN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
FIGURE 4A - LVPECL OUTPUT TERMINATION
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC-2V
FIN
FOUT
FIGURE 5A - RECOMMENDED SCHEMATIC LAYOUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The schematic of the ICS8431-11 layout example used in this layout guideline is shown in
Figure 5A. The ICS8431-11 recommended
PCB board layout for this example is shown in
Figure 5B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
VCC
C4
10uF
IN-
R1
50
VCCA
R1
125
C1
0.1uF
IN+
R2
84
VCC0
C6
0.01uF
TL1
Zo = 50 Ohm
VCC
U1
8431-11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
VEE
TEST_IO
VCC
VEE
nFOUT
FOUT
VCCO
NC
MR
VEE
VCCA
NC
nP_LOAD
VCC
XTAL1
XTAL2
Termination
B (not shown
in the layout)
R3
50
C3
0.01uF
R5
10
IN+
TL2
Zo = 50 Ohm
C2
0.1uF
X1
R3
125
Termination A
R2
50
IN-
R4
84
LAYOUT GUIDELINE
TERMINATION FOR LVPECL OUTPUTS
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