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參數(shù)資料
| 型號(hào)： | ICS8430BYI-71T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | ICS8430BYI-71T |
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8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
11
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads.This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
CCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
CCA as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location.While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
The traces with 50
Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination schemes can also be used but are not
shown in this example.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length be-
tween the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal
traces should not be routed near the crystal traces.
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8430BI-71
TL1N
C14
R1
TL1, TL21N are 50 Ohm
traces and equal length
TL1
C1
Close to the input
pins of the
receiver
GND
TL1N
C2
VCC
R7
PIN 1
X1
R3
VIA
VCCA
C11
C15
C16
R4
TL1
U1
R2
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| ICS8430CY-11T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430DY-111 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430DY-111LF | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8430DY-111LFT | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8430DY-111T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
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