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參數(shù)資料
| 型號(hào)： | ICS843002CY31 |
| 英文描述： | 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| 中文描述： | ⑩VCXO的700MHz的FEMTOCLOCKS基于頻率轉(zhuǎn)換和抖動(dòng)衰減器 |
| 文件頁(yè)數(shù)： | 17/27頁(yè) |
| 文件大小： | 274K |
| 代理商： | ICS843002CY31 |
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
17
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of
damping factor or the second pole imposed by C
. It does,
however, provide a useful approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO PLL
by the phase detector frequency, the following general rule
should be observed:
(Phase Detector) = Input Frequency ÷ XOIN
The PLL loop damping factor (DF) is determined by:
W
HERE
:
C
S
= Value of capacitor C
S
in loop filter in farads
D
ESCRIPTION
OF
THE
PLL S
TAGES
The ICS843002-31 is a two stage frequency multiplication
device, a VCXO PLL followed by a low phase noise
FemtoClock frequency multiplier. The VCXO uses an external
pullable crystal which can be pulled ±100ppm by the VCXO
PLL circuitry to phase lock it to the input reference frequency.
The output frequency of the VCXO PLL is equal to that of the
external pullable crystal, which is in the range of 17.5MHz to
25MHz. The loop bandwidth VCXO PLL is typically set in the
range of 10-250Hz which provides attenuation of input
reference clock jitter. Since the VCXO is a high-Q oscillator
circuit, it has low intrinsic output jitter and phase noise. The
VCXO PLL output clock is available from the VCLK pin.
The FemtoClock frequency multiplier has an effective
control bandwidth of about 800kHz which means it will track
the VCXO PLL clock output.
VCXO PLL L
OOP
R
ESPONSE
C
ONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the setting of the VCXO feedback divider value (XOFB)
and by the external loop filter components. A practical range
of loop bandwidth for many applications is 25Hz to 1kHz.
A bandwidth of less than 10Hz requires careful component
selection and possible metal shielding to prevent clock output
wander. A damping factor of 0.7 or greater should be used
to ensure loop stability. When a passband peaking of <0.1dB
is desired for SONET/SDH loop timing application, the
damping factor should be 6 or higher.
A PC base PLL bandwidth calculator is also under develop-
ment. For assistance with loop filter bandwidth and com-
ponent selection suggestions, please contact your ICS
sales representative.
S
ETTING
THE
VCXO PLL L
OOP
R
ESPONSE
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characteristics set by
the user. This includes the values of R
, C
, C
and R
as shown in the External VCXO PLL Components figure on
this page.
The VCXO PLL loop bandwidth is approximated by:
W
HERE
:
R
S
= Value of resistor R
S
in loop filter in ohms
I
CP
= Charge pump current in amps (see table on page 17)
K
= VCXO Gain in Hz/V (see table on page 18)
XOFB Divider = 1 to 8191
A
PPLICATION
I
NFORMATION
NBW (VCXO PLL) =
R
S
x I
CP
x K
O
2
π
x XOFB Divider
NBW (VCXO PLL)
≤
(Phase Detector)
20
DF (VCLK) = x
R
2
I
CP
x C
S
x K
O
XOFB Divider
1
2
3
64 63 62
LFR
LF
ISET
C
S
R
S
C
P
R
SET
optional
optional
F
IGURE
1. E
XTERNAL
VCXO PLL C
OMPONENTS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS843002CY-31 | 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002CY-31LF | 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002CY-31LFT | 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002CY-31T | 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002AGI-01 | FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843002CY-31 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002CY-31LF | 功能描述:IC SYNTHESIZER LVPECL 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:800MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS843002CY-31LFT | 功能描述:IC SYNTHESIZER LVPECL 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:800MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS843002CY-31T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002I | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
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