參數(shù)資料
型號(hào)： ICS843002CY31
英文描述： 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
中文描述： ⑩VCXO的700MHz的FEMTOCLOCKS基于頻率轉(zhuǎn)換和抖動(dòng)衰減器
文件頁數(shù)： 1/27頁
文件大?。?/td> 274K
代理商： ICS843002CY31
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843002-31 is a member of the
HiperClockS family of high performance clock
solutions from ICS. This monolithic device is a
high-performance, PLL-based synchronous
clock generator and jitter attenuation circuit. The
ICS843002-31 contains two clock multiplication stages that
are cascaded in series. The first stage is a VCXO-based PLL
that is optimized to provide reference clock jitter attenuation,
to be jitter tolerant, and to provide a stable reference clock
for the second multiplication stage. The second stage is the
proprietary ICS FemtoClockcircuit which is a high-frequency,
sub-picosecond clock multiplier.
The VCXO PLL has an on-chip VCXO circuit that uses an
external, inexpensive pullable crystal in the 17.5 to 25MHz
range. The PLL includes 13 bit reference and feedback
dividers supporting complex PLL multiplication ratios and
input reference clock rates as low as 2.3kHz. External loop
filter components are used (two resistors and two capacitors)
to achieve the low loop bandwidth needed for jitter atten-
uation of a recovered data clock.
The FemtoClock circuit can multiply the VCXO crystal
frequency by a factor of 28 or 32 (selectable) and provide a
clock output of up to 700MHz.
Clock Input/Output Configuration:
Clock Inputs - one differential pair, two singled ended
(mux selected)
Differential input pair can support LVPECL, LVDS,
LVHSTL, SSTL, HCSL or single-ended LVCMOS
or LVTTL levels
Singled ended inputs can support LVCMOS or
LVTTL levels
Clock Outputs, FemtoClockS two LVPECL pairs
(selectable output dividers)
Clock Output, VCXO – one single ended output
(at VCXO
crystal frequency)
Clock Output, other – VCXO reference clock
Example Applications:
SONET/SDH line card clock generator (up to 622.08MHz
for OC-48) using 8kHz frame clock as input reference
Jitter attenuation of a recovered communications clock
Complex-ratio clock frequency translation between
various communication protocols, such as:
For telecom, OC-12 to E3 rate conversion, 622.08MHz
to 34.368MHz, PLL ratio of 179/32
For digital video, ITU-R601 to SMPTE 252M/59.94,
27MHz to 74.17582MHz, PLL ratio of 250/91
P
IN
A
SSIGNMENT
F
EATURES
Outputs:
Two high frequency differential LVPECL outputs
Output frequency: up to 700MHz
One LVCMOS/LVTTL VCXO PLL output with output
enable
One Reference clock output with output enable
One LOCK detect output
Input mux supports 3 selectable inputs: one differential
input pair and two LVCMOS/LVTTL input clocks
13-bit VCXO PLL feedback and reference dividers provide
wide range of frequency translation ratio options
FemtoClock frequency multiplier supports rate of:
560MHz - 700MHz
‘Lock Detect’ output reports lock status of VCXO PLL
VCXO PLL circuit provides jitter attenuation with
loop bandwidth of 250Hz and below (user adjustable)
RMS phase jitter, random at 12kHz to 20MHz:
<1ps (design target)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockS
ICS
64-Lead TQFP, EPAD
10mm x 10mm x 1.0mm
package body
Y package
Top View
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
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7
8
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10
11
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ICS843002-31
V
EE
REF_CLK
VCLK
LOCK
V
CCO
_
CMOS
nQB
QB
V
EE
nQA
QA
V
CCO
_
PECL
MP
NPB0
NPB1
NPB2
V
CCA
LF1
LF0
ISET
V
EE
NV1
NV0
V
CC
MR
CLK0
nCLK0
OE_REF
CLK1
V
CC
SEL1
SEL0
CLK2
X
X
X
X
X
X
X
X
X
X
X
X
X
N
N
N
V
C
_
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
相關(guān)PDF資料
PDF描述
ICS843002CY-31 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31LF 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31LFT 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31T 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002AGI-01 FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS843002CY-31 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ FEMTOCLOCKS? VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002CY-31LF 功能描述:IC SYNTHESIZER LVPECL 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件
ICS843002CY-31LFT 功能描述:IC SYNTHESIZER LVPECL 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件
ICS843002CY-31T 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
ICS843002I 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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