參數(shù)資料
型號: ICS83940DYI-01LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/18頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:18 32-LQFP
標準包裝: 250
系列: HiPerClockS™
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:18
差分 - 輸入:輸出: 是/無
輸入: CML,LVCMOS,LVPECL,LVTTL,SSTL
輸出: LVCMOS,LVTTL
頻率 - 最大: 250MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
其它名稱: 83940DYI-01LF
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
7
2010 Integrated Device Technology, Inc.
ICS83940I-01 Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 150MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, same frequency and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
175
MHz
tPLH
Propagation
Delay
PCLK, nPCLK; NOTE 1, 5
≤ 150MHz
1.7
3.2
ns
LVCMOS_CLK; NOTE 2, 5
≤ 150MHz
1.7
3.0
ns
Propagation
Delay
PCLK, nPCLK; NOTE 1, 5
> 150MHz
1.6
3.4
ns
LVCMOS_CLK; NOTE 2, 5
> 150MHz
1.8
3.3
ns
tjit
Additive Phase
Jitter, RMS; Refer
to Additive Phase
Jitter Section
PCLK, nPCLK
155.52MHz, Integration
Range: 12kHz – 20MHz
0.199
ps
LVCMOS_CLK
0.137
ps
tsk(o)
Output Skew; NOTE 3, 5
Measured on the Rising Edge
@ VDDO/2
150
ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
≤ 150MHz
1.5
ns
LVCMOS_CLK
≤ 150MHz
1.3
ns
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
> 150MHz
1.8
ns
LVCMOS_CLK
> 150MHz
1.5
ns
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
Measured on the Rising Edge
@ VDDO/2
975
ps
LVCMOS_CLK
875
ps
tR / tF
Output Rise/Fall Time
20% to 80%
300
800
ps
odc
Output Duty Cycle
≤ 150MHz
45
55
%
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