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參數(shù)資料
| 型號： | ICS8312AYLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFF 1:12 250MHZ 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 無/無 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVTTL |
| 頻率 - 最大： | 250MHz |
| 電源電壓： | 1.6 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1249 (CN2011-ZH PDF) |
| 其它名稱： | 800-1111 8312AYLF |
ICS8312
LOW SKEW, 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER
IDT / ICS LVCMOS/LVTTL FANOUT BUFFER
10
ICS8312AY REV. D JULY 3, 2008
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependant on the input source and measurement equipment.
Additive Phase Jitter, 3.3V @ 100MHz
12kHz to 20MHz = 0.037ps (typical)
SSB
Phas
e
Noise
dBc/Hz
Offset from Carrier Frequency (Hz)
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| ICS8312AYLFT | 功能描述:IC CLK BUFF 1:12 250MHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS8312AYT | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER |
| ICS8312I | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER |
| ICS8316 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS |
| ICS8316AK | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS |
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