參數(shù)資料
型號: ICS8312AYLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/18頁
文件大?。?/td> 0K
描述: IC CLK BUFF 1:12 250MHZ 32-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: HiPerClockS™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:12
差分 - 輸入:輸出: 無/無
輸入: LVCMOS,LVTTL
輸出: LVCMOS,LVTTL
頻率 - 最大: 250MHz
電源電壓: 1.6 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 1249 (CN2011-ZH PDF)
其它名稱: 800-1111
8312AYLF
ICS8312
LOW SKEW, 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER
IDT / ICS LVCMOS/LVTTL FANOUT BUFFER
7
ICS8312AY REV. D JULY 3, 2008
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tpLH
Propagation Delay, Low to High; NOTE 1
≤ 250MHz
1.2
1.9
2.5
ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.037
ps
tsk(o)
Output Skew; NOTE 2, 5
125
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
800
ps
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
200
700
ps
odc
Output Duty Cycle
≤ 200MHz
45
55
%
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tpLH
Propagation Delay, Low to High; NOTE 1
≤ 250MHz
1.4
2.3
3.2
ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.022
ps
tsk(o)
Output Skew; NOTE 2, 5
150
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
1.1
ns
tR / tF
Output Rise/Fall Time; NOTE 5
20% to 80%
200
700
ps
odc
Output Duty Cycle
≤ 150MHz
45
55
%
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