參數(shù)資料
型號(hào): ICS8308AGILF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:8 24-TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: HiPerClockS™
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/無
輸入: HCSL,LVCMOS,LVDS,LVHSTL,LVPECL,LVTTL,SSTL
輸出: LVCMOS,LVTTL
頻率 - 最大: 350MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
其它名稱: 8308AGILF
ICS8308AGILF-ND
ICS8308AGI REVISION C APRIL 4, 2013
10
2013 Integrated DeviceTechnology, Inc.
ICS8308I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
APPLICATION INFORMATION
Figure 1 shows how a differential input can be wired to accept
single ended levels.The reference voltage VREF = VDD/2 is generated
by the bias resistors R1 and R2. The bypass capacitor (C1) is
used to help filter noise on the DC bias. This bias circuit should
be located as close to the input pin as possible. The ratio of R1
and R2 might need to be adjusted to position the VREF in the
center of the input voltage swing. For example, if the input clock
swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted
to set VREF at 1.25V. The values below are for when both the single-
ended swing and VDD are at the same voltage. This configuration
requires that the sum of the output impedance of the driver (Ro)
and the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
FIGURE 1. RECOMMENDED SCHEMATIC FOR WIRING A DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
impedance. For most 50 applications, R3 and R4 can be 100
Ω.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of
the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
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ICS8308I 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer
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