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參數(shù)資料
| 型號(hào)： | ICS8302AMT |
| 英文描述： | LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER |
| 中文描述： | 低偏移，1對2的LVCMOS / LVTTL扇出緩沖器 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 252K |
| 代理商： | ICS8302AMT |
4
ICS932S203
0601E—12/22/04
Byte 0: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull
the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the
chip is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
Byte 1: Control Register
t
B
#
n
P
e
m
a
N
D
W
1
X
X
P
e
p
y
T
n
o
p
c
s
e
D
0
1
2
t
t
t
-
5
0
)
e
h
h
v
s
s
s
w
a
s
v
s
S
H
M
6
6
v
s
e
e
R
e
R
e
R
d
H
n
e
R
(
C
V
=
0
R
(
(
5
4
0
1
S
S
F
F
R
R
p
p
#
u
u
r
w
o
r
w
o
T
S
_
C
p
p
n
n
o
o
P
d
d
e
m
e
m
a
u
v
a
s
s
n
n
h
0
1
S
S
s
F
F
f
f
e
R
D
W
P
e
e
u
v
u
v
:
d
o
n
o
e
e
m
d
3
t
4
3
#
P
O
T
S
_
C
P
3
X
R
P
O
f
e
e
e
e
m
e
e
,
H
e
4
t
-
1
)
t
5
t
5
3
H
C
V
/
_
6
6
V
3
0
W
R
z
H
M
8
4
H
H
M
M
8
6
4
6
=
z
1
6
t
-
0
)
7
t
-
d
d
a
e
S
a
n
E
e
0
W
R
n
O
d
a
e
S
=
1
,
O
d
a
e
S
=
0
t
B
#
n
P
e
K
K
K
K
K
K
m
L
C
C
C
U
C
U
C
U
C
U
a
N
U
U
D
W
P
e
p
y
T
n
o
p
c
s
e
D
0
t
1
5
,
5
0
0
1
1
2
2
T
C
T
C
T
C
P
P
P
P
P
P
C
C
C
C
C
C
L
L
L
L
L
1
W
R
d
e
a
n
E
=
1
d
e
a
s
D
=
0
1
t
8
4
,
4
1
W
R
d
e
a
n
E
=
1
d
e
a
s
D
=
0
2
t
4
4
,
4
1
W
R
d
e
a
n
E
=
1
d
e
a
s
D
=
0
3
4
5
t
t
t
1
8
4
5
4
4
,
5
,
4
,
4
0
0
0
-
-
-
d
d
d
e
e
e
v
s
v
s
v
s
e
e
e
R
R
R
6
t
4
5
,
5
3
3
0
T
C
L
K
K
E
L
L
S
C
C
T
U
U
L
U
P
P
C
C
M
1
W
R
d
e
a
n
E
=
1
d
e
a
s
D
=
0
7
t
3
4
X
R
0
L
E
S
T
L
U
M
f
e
u
v
t
e
c
e
h
s
e
R
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