參數(shù)資料
型號(hào): ICS680G-01T
英文描述: Networking Clock Synthesizer and Zero Delay Buffer
中文描述: 網(wǎng)絡(luò)時(shí)鐘合成器和零延遲緩沖器
文件頁(yè)數(shù): 8/8頁(yè)
文件大?。?/td> 107K
代理商: ICS680G-01T
Networking Clock Synthesizer and Zero Delay Buffer
MDS 680-01 F
8
Revision 020305
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS680-01
Revision History
Rev.
Originator
Date
Description of Change
D
P.Griffith
10/01/04
Removed power supply ramp-up time spec; added trinary input specs to DC chars; added
a second Output Low Voltage spec; updated Supply Current specs from 50 to 32 mA, and
50 to 300 uA; changed pull-down resistor value from 525 to 250 kohms; changed Output
Rise/Fall times from 1 to 1.5 ns
E
P.Griffith
12/21/04
Released as standard product from custom device.
F
J. Sarma
02/03/05
Add LF ordering info.
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