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參數(shù)資料
| 型號： | ICS673M-01T |
| 英文描述： | PLL Building Block |
| 中文描述： | 鎖相環(huán)積木 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 73K |
| 代理商： | ICS673M-01T |
ICS673-01
PLL Building Block
MDS 673-01 D
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800tel www.icst.com
4
Revision 022500
Printed 11/15/00
Figure 1. Typical Configuration; Generating 40 MHz from 200 kHz
Explanation of Operation
REFIN
FBIN
CHGP VCOIN
CAP
CLK1
CLK2
SEL
OE
+3.3 or 5 V
200kHz
40 MHz
20 MHz
Digital Divider
or ICS674-01
÷100
C2
C1
RZ
PD
ICS673-01
VDD
GND
0.1μF
200kHz
The ICS673 is a PLL building block circuit that
includes an integrated VCO with a wide operating
range. While it can easily lock MHz frequencies to
other MHz frequencies, it is especially designed
for starting with a kHz frequency and generating a
frequency-locked MHz clock. Refer to Figure 1
below and to the Block Diagram on page 1.
The phase/frequency detector compares the falling
edges of the clocks connected to FBIN and
REFIN. It then generates an error signal to the
charge pump, which produces a charge
proportional to this error. The external loop filter
integrates this charge, producing a voltage that
then controls the frequency of the VCO. This
process continues until the edges of FBIN are
aligned with the edges of the REFIN clock, at
which point the output frequency will be locked to
the input frequency.
External Components
The ICS673 requires a minimum number of
external components for proper operation. A
decoupling capacitor of 0.01μF should be
connected between VDD and GND as close to the
ICS673 as possible. A series termination resistor of
33
may be used for each clock output. Two
ceramic capacitors and a resistor are needed for the
external loop filter; calculations to determine the
proper values are shown on the following pages.
The capacitors must have very low leakage,
therefore high quality ceramic capacitors are
recommended. DO NOT use any type of polarized
or electrolytic capacitor. Ceramic capacitors should
have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R; these and other
ceramics which have piezoelectric properties allow
mechanical vibration in the system to increase the
output jitter because the mechanical energy is
converted directly to voltage noise on the VCO
input.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS674-01 | 制造商:ICS 制造商全稱:ICS 功能描述:User Configurable Divider |
| ICS674R-01 | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS674R-01I | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS674R-01ILF | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS674R-01ILFT | 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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