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參數(shù)資料
| 型號： | ICS670-01 |
| 英文描述： | Low Phase Noise Zero Delay Buffer and Multiplier |
| 中文描述： | 低相位噪聲零延遲緩沖器和乘法器 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 84K |
| 代理商： | ICS670-01 |
ICS670-01
Low Phase Noise Zero Delay Buffer and Multiplier
MDS 670-01 B
Integrated Circuit Systems 525 Race Street San Jose CA95126(408) 295-9800telhttp://www.icst.com
2
Revision 100900
Printed 11/15/00
Pin Descriptions
Pin Assignment
ICS670-01
0=connect directly to ground
1=connect directl to VDD
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK2 (and FBCLK)
Low (Power down entire chip)
Input x1.333
Input x6
Input x1.5
Input x3.333
Input x2.50
Input x4
Input x1
Input x2.333
Input x2.666
Input x12
Input x3
Input x10
Input x5
Input x8
Input x2
Input Range (MHz)
-
18 - 120
5 - 26.67
16.67 - 107
7.5 - 48
10 - 64
6 - 40
25 - 160
11 - 69
10 - 60
5 - 13.33
8 - 53.33
5 - 16
6 - 32
5 - 20
12 - 80
Multiplier Select Table
1
2
3
4
5
6
7
8
9
16
15
10
11
12
13
14
S2
S3
ICLK
GND
S0
S1
GND
OE1
FBIN
FBCLK
VDD
VDD
CLK2
OE2
VDD
GND
Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; CI = clock input.
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
VDD
VDD
VDD
CLK2
OE2
FBCLK
OE1
FBIN
ICLK
S3
S2
S1
S0
GND
GND
GND
Type
P
P
P
O
I
O
I
CI
CI
I
I
I
I
P
P
P
Description
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Output clock enable 2. Tri-states the clock 2 output when low.
Clock ouput from VCO. Output frequency equals the input frequency times multiplier.
Output clock enable 1. Tri-states the feedback clock output when low.
Feedback clock input.
Clock input. Connect to a 5 - 160 MHz clock.
Multiplier select pin 3. Determines outputs per table above. Internal pull-up.
Multiplier select pin 2. Determines outputs per table above. Internal pull-up.
Multiplier select pin 1. Determines outputs per table above. Internal pull-up.
Multiplier select pin 0. Determines outputs per table above. Internal pull-up.
Connect to ground.
Connect to ground.
Connect to ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS670M-01I | Low Phase Noise Zero Delay Buffer and Multiplier |
| ICS670M-01IT | Low Phase Noise Zero Delay Buffer and Multiplier |
| ICS670M-01T | Low Phase Noise Zero Delay Buffer and Multiplier |
| ICS671-03 | 3.3 Volt Zero Delay, Low Skew Buffer |
| ICS671M-03I | 3.3 Volt Zero Delay, Low Skew Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS670-02 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW PHASE NOISE, ZERO DELAY BUFFER AND MULTIPLIER |
| ICS670-03 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW PHASE NOISE, ZERO DELAY BUFFER AND MULTIPLIER |
| ICS670-04 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW PHASE NOISE, ZERO DELAY BUFFER AND MULTIPLIER |
| ICS670M-01 | 功能描述:IC BUFFER/MULTIPLIER ZD 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS670M-01I | 功能描述:IC BUFFER/MULTIPLIER ZD 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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