參數(shù)資料
型號(hào): ICS553MLFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFFER 1:4 200MHZ 8-SOIC
產(chǎn)品培訓(xùn)模塊: Clock Distibution and Generation 1.0
標(biāo)準(zhǔn)包裝: 2,500
系列: ClockBlocks™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無(wú)/無(wú)
輸入: CMOS
輸出: CMOS
頻率 - 最大: 200MHz
電源電壓: 2.375 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
其它名稱: 553MLFT
ICS553
LOW SKEW 1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
IDT LOW SKEW 1 TO 4 CLOCK BUFFER
2
ICS553
REV N 051310
Pin Assignment
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 F should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible.
A 33
Ω series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS553 is capable of, careful attention must be paid to board
layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30
Ω series termination
on one output (with 33
Ω on the others) will cause at least 15 ps of skew.
1
2
3
VD D
4
Q0
Q1
Q3
GN D
Q2
IC L K
8
7
6
5
OE
8- p i n S O I C
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
VDD
Power
Connect to +2.5 V, +3.3 V or +5.0 V.
2
Q0
Output
Clock output 0.
3
Q1
Output
Clock output 1.
4
GND
Power
Connect to ground.
5
ICLK
Input
Clock input, 5 V tolerant input.
6
Q2
Output
Clock Output 2.
7
Q3
Output
Clock Output 3.
8
OE
Input
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
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