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參數(shù)資料
| 型號： | ICS387G-XX-LF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 71K |
| 代理商： | ICS387G-XX-LF |
MDS 387 A
3
Revision 050401
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 ( 408) 295-9800 www.icst.com
ICS387
Quad PLL Quick Turn Clock Synthesizer
PRELIMINARY INFORMATION
External Components / Crystal Selection
The ICS387 requires a 0.01F decoupling capacitor to be connected between VDD and GND on pins 5 and 6, and
another between pins 12 and 11. These must be connected close to the ICS387 to minimize lead inductance. No
external power supply filtering is required for this device. A 33
series terminating resistor can be used next to
each CLK pin. For a crystal input, a parallel resonant, fundamental mode crystal should be used. Crystal capacitors
must be connected from each of the pins X1 and X2 to Ground. The value (in pF) of these crystal caps should equal
(CL-6pf)*2, where CL is the crystal load capacitance in pF. As an example, for a crystal with 16 pF load capacitance,
each crystal capacitor would be 20 pF [(16 - 6pf)*2 = 20].
For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either X1 or X2).
Frequency Select Table
The ICS387 can be configured so that one PLL provides up to 8 frequency selections. For example, CPU
frequencies of 66.7 MHz, 100.0 MHz, 133.3 MHz, and 166.7 MHz could be included. This information should be
indicated on the Order Form when the ICS387 is initially defined.
Device Configuration
The ICS387 QTClock provides the facility for up to 5 clock outputs. The outputs are derived from either the
reference input or from one of the 4 PLLs. All chip functions are controlled from an OTP ROM which has 3 input
control lines (S2, S1, S0), giving a total of 8 address locations. Each address location gives control of the following:
1) Each output can be turned off individually
2) The internal dividers for each PLL are controlled to generate any required frequency.
3) Each PLL can be turned off (powered down) individually.
4) The output divide and control logic can be configured to bring the appropriate clock to the correct pin.
5) Up to four low skew copies of the same clock can be enabled.
This chip architecture provides the user with unrivaled flexibility. For example, one of the input pins could be used
to control the power of the chip by shutting down PLLs and outputs when not used. The second and third could
be used to change the output clock frequencies.
The specification is complete when the ICS387 QTClock Order Form accompanies this data sheet. The order form
lists the input and CLK actual frequencies, as well as any other available options. This unique configuration is given
a two character alphanumeric programming code (ICS387-xx), which must be specified when referring to samples
or ordering parts.
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