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參數(shù)資料
| 型號： | ICS387G-XX-LF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 71K |
| 代理商： | ICS387G-XX-LF |
MDS 387 A
1
Revision 050401
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 ( 408) 295-9800 www.icst.com
ICS387
Quad PLL Quick Turn Clock Synthesizer
PRELIMINARY INFORMATION
Packaged as 16 pin TSSOP
Quick turn frequency programming allows
samples as quickly as one day
Up to 2 outputs can be low-skew
Can include 8 selectable output frequencies
Up to 3 reference outputs
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3V
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Duty cycle of 45/55
Operating voltages of 3.3 V or 5 V
Advanced, low power CMOS process
The ICS387 QTClock generates up to 5 high quality,
high frequency clock outputs including a reference
from a low frequency crystal or clock input. It is designed
to replace crystals and crystal oscillators in most
electronic systems. The ICS387 contains a One Time
Programmable (OTP) ROM which is factory programmed
with PLL divider values to output a broad range of
frequencies up to 200 MHz, allowing customer
requests for different frequencies to be shipped in 1-3
days. Programming features include a selectable
frequency table and up to 2 low-skew outputs.
Using Phase-Locked-Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
Block Diagram
Description
Features
Crystal
or clock
input
OTP
ROM
with PLL
Divider
Values
PLLA
PLLB
Divide
Logic
and
Output
Control
CLK1
CLK2
CLK3
CLK4
CLK5
PLLC
PDTS (all outputs and PLLs)
X1/ICLK
Crystal
Oscillator
X2
Capacitors are required with a crystal input.
S2:S0
3
PLLD
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