參數(shù)資料
型號: ICS309RIT
英文描述: SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTHESIZER
中文描述: 串行可編程三重不銹鋼VERSACLOCK合成器鎖相環(huán)
文件頁數(shù): 1/8頁
文件大?。?/td> 132K
代理商: ICS309RIT
ICS309
MDS 309 G
1
Revision 122704
Integrated Circuit Systems
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
S
ERIAL
P
ROGRAMMABLE
T
RIPLE
PLL SS V
ERSA
C
LOCK
S
YNTHESIZER
Description
The ICS309 is a versatile serially-programmable, triple
PLL with spread spectrum clock source. The ICS309
can generate any frequency from 250kHz to 200 MHz,
and up to 6 different output frequencies simultaneously.
The outputs can be reprogrammed on-the-fly, and will
lock to a new frequency in 10 ms or less.
To reduce system EMI emissions, spread spectrum is
available that supports modulation frequencies of
31 kHz and 120 kHz, as well as modulation amplitudes
of +/-0.25% to +/-2.0%. Both center and down-spread
options are available.
The device includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS309 default for non-programmed start-up are
buffered reference clock outputs on all clock output
pins.
ICS’ VersaClock
TM
programming software allows the
user to configure up to 9 outputs with target
frequencies, spread spectrum capabilities or buffered
reference clock outputs. The VersaClock
TM
software
automatically configures the PLLs for optimal overall
performance.
Features
Packaged in 20-pin SSOP (QSOP)
Highly accurate frequency generation
M/N Multiplier PLL: M = 1..2048, N = 1..1024
Serially programmable: user determines the output
frequency via a 3-wire interface
Spread Spectrum frequency modulation for reduced
system EMI
Center or Down Spread up to 4% total
Selectable 32 kHz and 120 kHz modulation
Eliminates need for custom quartz oscillators
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 3 - 50 MHz
Output clock frequencies up to 200 MHz
Operating voltage of 3.3 V
Up to 9 reference clock outputs
Power down tri-state mode
Very low jitter
Block Diagram
Crystal
Oscillator
PLL1 with
Spread
Spectrum
GND
2
3
VDD
PDTS
PLL2
PLL3
Divide
Logic
and
Output
Enable
Control
CLK1
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
X2
Crystal or
clock input
External capacitors are
required with a crystal input.
X1/ICLK
SCLK
DATA
STROBE
相關(guān)PDF資料
PDF描述
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