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參數(shù)資料
| 型號： | ICS291PGLF |
| 元件分類： | XO, clock |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.173 INCH, ROHS COMPLIANT, TSSOP-20 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 167K |
| 代理商： | ICS291PGLF |
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 291 C
3
Revision 062205
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS291
PRELIMINARY INFORMATION
External Components
The ICS291 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS291 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL -6 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
ICS291 Configuration Capabilities
The architecture of the ICS291 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 1024 and N = 1 to
32,895.
The ICS291 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
Output Drive Control
The ICS291 has two output drive settings. For
VDDO=VDD, low drive should be selected when
outputs are less than 100 MHz. High drive should be
selected when outputs are greater than 100 MHz.
For VDDO<2.8 V, high drive should be selected for all
output frequencies.
(Consult the AC Electrical Characteristics for output
rise and fall times for each drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
Spread Spectrum Modulation
The ICS291 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
frequencies; thus, lowering a system’s electromagnetic
interference (EMI). The modulation rate is the time from
transitioning from a minimum frequency to a maximum
frequency and then back to the minimum.
OutputFreq
REFFreq
M
N
-----
=
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| ICS291PGLFT | 功能描述:IC CLK SYNTH TRPL PLL 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS291PGT | 功能描述:IC CLK SYNTH TRPL PLL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS300 | 制造商:ICS 制造商全稱:ICS 功能描述:QTClock⑩ Quick Turn Clock Synthesizer |
| ICS3002AI01L | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
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