參數(shù)資料
型號(hào)： ICS1894KI-40LFT
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 34/53頁(yè)
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 40QFN
標(biāo)準(zhǔn)包裝： 1
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII，RMII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-VFQFPN（6x6）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 800-2032-6
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
4
ICS1894-40
REV K 022412
Notes:
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY to the MAC.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
28
SPEED/
TXCLK
IO/Ipu
10M/100M select as input (during power on reset and hardware reset)
Transmit clock as output in MII mode
29
TXEN
Input
Transmit enable for both RMII and MII modes
30
TXD0
Input
Transmit data Bit 0 for both RMII and MII modes
31
VDDD
Power
Core Power Supply
32
LED3
IO/Ipu
LED3 output
33
TXD1
Input
Transmit data Bit 1for both RMII and MII modes
34
TXT2
Input
Transmit data Bit 2 for MII mode
35
TXD3
Input
Transmit data Bit 3 for MII mode
36
REF_OUT
Output
25 MHz crystal output
37
REF_IN
Input
25 MHz crystal (or clock) input for MII mode. 50MHz clock input for RMII mode
38
P4/LED2
IO/Ipu
PHY address Bit 4 as input (always latched high during power on reset and
hardware reset) and LED # 2 as output
39
P0/LED0
IO
PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
40
P1/ISO/LED1
IO
PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Pin
Number
Pin
Name
Pin
Type
Pin Description
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