參數(shù)資料
型號: ICS1893BKLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 28/133頁
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 56-VQFN
標(biāo)準(zhǔn)包裝: 1,000
系列: PHYceiver™
類型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-VFQFP-EP(8x8)
包裝: 帶卷 (TR)
其它名稱: 1893BKLFT
Chapter 9 DC and AC Operating Conditions
ICS1893BF, Rev. F, 5/13/10
May, 2010
123
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The
time periods consist of timings of signals on the following pins:
TP_RX (that is, TP_RXP and TP_RXN)
CRS
COL
Figure 9-15 shows the timing diagram for the time periods.
The IEEE maximum is 20 bit times.
The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 9-15. 100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram
Table 9-21. 100M MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Period
Parameter
Conditions
Min.
Typ. Max.
Units
t1
First Bit of /J/ into TP_RX to CRS Assert
10
14
Bit times
t2
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert
Half-Duplex Mode
9
13
Bit times
t3
First Bit of /T/ into TP_RX to CRS
De-Assert
–13
18
Bit times
t4
First Bit of /T/ Received into TP_RX to
COL De-Assert
Half-Duplex Mode
13
18
Bit times
t1
t2
t3
t4
First bit
First bit of /T/
Shown
unscrambled.
TP_RX
CRS
COL
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