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參數(shù)資料
| 型號(hào)： | ICS1893BFILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 67/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類(lèi)型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 1893BFILF |
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Chapter 6 Functional Blocks
ICS1893BF, Rev. F, 5/13/10
May, 2010
39
ICS1893BF Data Sheet Rev. F - Release
All rights reserved.
6.3.6 4B/5B Encoding/Decoding
The 4B/5B encoding methodology maps each 4-bit nibble to a 5-bit symbol (also called a “code group”).
There are 32 five-bit symbols, which include the following:
Of the 32 five-bit symbols, 16 five-bit symbols are required to represent the 4-bit nibbles.
The remaining 16 five-bit symbols are available for control functions. The IEEE Standard defines 6
symbols for control, and the remaining 10 symbols of this grouping are invalid. The 6 control symbols
include the following:
– /H/, which represents a Halt, also used to signify a Transmit Error
– /I/, which represents an IDLE
– /J/, which represents the first symbol of the Start-of-Stream Delimiter (SSD)
– /K/, which represents the second symbol of the Start-of-Stream Delimiter (SSD)
– /T/, which represents the first symbol of the End-of-Stream Delimiter (ESD)
– /R/, which represents the second symbol of the End-of-Stream Delimiter (ESD)
If the ICS1893BF PCS receives:
– One of the 10 undefined symbols, it sets its QuickPoll Detailed Status Register’s Invalid Symbol bit
(bit 17.7) to logic one.
– A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6)
to logic one.
Note: An STA can force the ICS1893BF to transmit symbols that are typically classified as invalid, by
both (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic one
and (2) asserting the associated TXER signal. For more information, see Section 7.11.7, “Invalid
6.4 Functional Block: 100Base-TX TP-PMD Operations
The ICS1893BF supports both 10Base-T and 100Base-TX operations. For 100Base-TX operations, the
TP-PMD module performs stream-cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level,
multi-level transition) in compliance with the ANSI Standard X3.263: 199X FDDI TP-PMD as defined in the
specification for 100Base-TX Twisted-Pair Physical Media Dependent (TP-PMD) Sublayer. The
ICS1893BF’s TP-PMD also performs DC restoration (that is, baseline wander correction) and adaptive
equalization on the received signals.
Note:
1. For an overview of 100Base-TX operations, see Section 4.5, “100Base-TX Operations”.
2. For more information on the Twisted-Pair Interface, see Section 5.3, “Twisted-Pair Interface”.
6.4.1 100Base-TX Operation: Stream Cipher Scrambler/Descrambler
When the ICS1893BF is operating in 100Base-TX mode, it employs a stream cipher
scrambler/descrambler that complies with the ANSI Standard X3.263: 199X FDDI TP-PMD. The purpose of
the stream cipher scrambler is to spread the transmission spectrum to minimize electromagnetic
compatibility problems. The stream cipher descrambler restores the received serial bit stream to its
unscrambled form.
The ICS1893BF “seeds” (that is, initializes) the Transmit Stream Cipher Shift register by using the
ICS1893BF PHY address from Table 7-16, which minimizes crosstalk and noise in repeater applications.
The MAC Interface bypasses the stream cipher scrambler/descrambler when in the 100M Symbol Interface
mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1894KI-32LF | PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-40LFT | PHYCEIVER LOW PWR 3.3V 40QFN |
| ID82C55A | IC I/O EXPANDER 24B 40DIP |
| ID82C82 | IC DRIVER BUS OCT LATCHING 20DIP |
| ID82C86H | IC TRANSCEIVER OCT BUS 20-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893BFILFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFIT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893BFLF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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