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參數(shù)資料
| 型號： | ICS1574BMLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PROGR LASER 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器，時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1574BMLFT |
5
ICS1574B
N
I
A
G
O
C
VY
C
N
E
U
Q
E
R
F
X
A
M
4z
H
M
0
1
5z
H
M
0
2
6z
H
M
0
3
7z
H
M
0
4
Reference Oscillator
and Crystal Selection
The ICS1574B has circuitry on-board to implement a
Pierce oscillator with the addition of only one external
component, a quartz crystal. Pierce oscillators operate the
crystal
in
anti- (also called parallel-) resonant mode. See the AC
Characteristics for the effective capacitive loading to
specify when ordering crystals.
Series-resonant crystals may also be used with the
ICS1574B. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the
can (typically 0.025 – 0.05%).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend
that the crystal be mounted as closely as possible to the
package. Avoid routing digital signals or the ICS1574B
outputs underneath or near these traces. It is also desirable
to ground the crystal can to the ground plane, if possible.
If an external reference frequency source is to be used with
the ICS1574B, it is important that it be jitter-free. The ris-
ing and falling edges of that signal should be fast and free
of noise for best results.
The loop phase can be locked to either the rising or falling
edges of the XTAL1 input signals, and is controlled by
Bit 56.
Power-On Initialization
The ICS1574B has an internal power-on reset circuit that
performs the following functions:
1) Selects the modulus of the PCLK divider to
be four (4).
2) Sets the multiplexer to pass the reference
frequency to PCLK divider input.
These functions should allow initialization for most appli-
cations that cannot immediately provide for register
programming upon system power-up.
Because the power-on reset circuit is on the VDD supply,
and because that supply is filtered, care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD sup-
ply reaches 4 volts.
Programming Notes
VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
Divider Range: For best results in normal situations
keep the reference divider modulus as short as possible
(for a frequency at the output of the reference divider in
the few hundred kHz to several MHz range). If you
need to go to a lower phase comparator reference fre-
quency (usually required for increased frequency
accuracy), that is acceptable, but jitter performance will
suffer somewhat.
VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as
shown here:
Phase Detector Gain: For most applications and divider
ranges, set P [1, 0] = 10 and set P [2] = 1. Under some
circumstances, setting the P [2] bit “on” can reduce
jitter. During operation at exact multiples of the crystal
frequency, P[2] bit = 0 may provide the best jitter per-
formance.
Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1574B supports
this through a register programmable mode, AUX-EN.
When this mode is set, a register bit directly controls the
logic level of the PCLK pin. This mode is activated when
the S[0] and S[1] bits are both set to logic 1. See Register
Mapping for details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1574BMT | 功能描述:IC CLOCK GEN PROGR LASER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1577N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| ICS-16 | 制造商:MAXCONN 功能描述: |
| ICS162834 | 制造商:ICS 制造商全稱:ICS 功能描述:18-Bit 3.3V Registered Buffer |
| ICS162834AG-T | 制造商:ICS 制造商全稱:ICS 功能描述:18-Bit 3.3V Registered Buffer |
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