- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360743 > ICS1572 GT 7C 7#16S SKT RECP WALL RM PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS1572 |
| 英文描述： | GT 7C 7#16S SKT RECP WALL RM |
| 中文描述： | 用戶可編程的差分輸出圖形時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 276K |
| 代理商： | ICS1572 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
BIT(S)
BIT REF.
DESCRIPTION
13-14
S[0]..S[1]
PLL post-scaler/test mode select bits.
S[1] S[0]
0
DESCRIPTION
0
Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider drives
the LOAD output which, in turn, drives the N2 divider.
Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
0
1
1
0
1
1
15
AUX_CLK
When in the AUXEN clock mode, this bit controls the differential outputs.
16
AUX_N1
When in the AUXEN clock mode, this bit controls the N1 output (and
consequently the N2 output according to its programming).
Sets the modulus of the N2 divider. The input of the N2 divider is the
output of the N1 divider in all clock modes except AUXEN.
Sets the gain of VCO.
17-24
28
25-27
N2[0]..N2[7]
N2[8]
V[0]..V[2]
V[2]
V[1]
V[0]
VCO GAIN
(MHz/VOLT)
30
45
60
80
1
1
1
1
0
0
1
1
0
1
0
1
29-30
P[0]..P[1]
Sets the gain of the phase detector according to this table.
P[1]
0
0
1
1
P[0]
0
1
0
1
GAIN (uA/radian)
0.05
0.15
0.5
1.5
31
RESERVED
Set to zero.
32
P[2]
Phase detector tuning bit. Should normally be set to one.
ICS1572
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1572M-101 | GT 4C 4#12 PIN RECP WALL RM |
| ICS1572M-301 | GT 4C 4#12 SKT RECP WALL RM |
| ICS1574B | GT 5C 5#12 PIN RECP WALL RM |
| ICS1574BEB | GT 5C 5#12 SKT RECP WALL RM |
| ICS1574BM | GT 10C 10#16 PIN RECP WALL RM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1572M101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1572M-101 | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1572M301 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1572M-301 | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1574B | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Laser Engine Pixel Clock Generator |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。