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參數(shù)資料
| 型號： | ICS1567-742 |
| 英文描述： | Differential Output Video Dot Clock Generator |
| 中文描述： | 差分輸出視頻點時鐘發(fā)生器 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 161K |
| 代理商： | ICS1567-742 |
AC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CLK and CLK TIMING
40
Duty Cycle
Frequency Error
Rise Time
Fall Time
VCO Frequency
PLL Acquire Time
T
HIGH
60
0.5
2
2
180
%
%
ns
ns
3, 4, 9
T
r
T
f
5, 9
5, 9
1
F
VCO
T
LOCK
20
MHz
uS
500
LD* TIMING
40
Duty Cycle
Load Frequency
Rise Time
Fall Time
T
HIGH
F
LOAD
T
r
T
f
60
60
2
2
%
6
MHz
ns
ns
7, 8
7, 8
REFERENCE INPUT CLOCK
F
XTAL
5
C
PAR
Crystal Frequency
Crystal Oscillator
Loading Capacitance
XTAL1 High Time
XTAL1 Low Time
Rise Time
Fall Time
20
MHz
pF
20
T
XHI
T
XLO
T
r
T
f
8
8
ns
ns
ns
ns
2
2
10
10
2, 7
2, 7
DIGITAL INPUTS
10
10
20
PIPELINE DELAY RESET
Frequency Select Setup Time
Frequency Select Hold Time
Strobe Pulse Width
1
2
3
ns
ns
ns
10
10
10
Reset Activation
Reset Duration
Restart Delay
4
5
6
2*T
CLK
ns
ns
ns
10
10
10
4*T
CLK
-1*T
CLK
+1.5*T
CLK
Notes
:
1.
Use of the post-divider is required for frequencies lower than 20 MHz on CLK and CLK outputs. Use of the
post-divider is recommended for output frequencies lower than 65 MHz.
Values for XTAL1 driven by an external clock
Duty Cycle for Differential Output (CLK- CLK)
Duty cycle measured at VOD/2 for Differential CLK Output
Rise and fall time between 20% and 80% of VOD
Duty cycle measured at 1.4V for TTL I/O
Rise and fall time between 0.8 and 2.0 VDC for TTL I/O
Output pin loading = 15 pF
See Figure 3.
10. See Figure 4.
2.
3.
4.
5.
6.
7.
8.
9.
ICS1567
8
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICS1567M-742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1572 | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1572M101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1572M-101 | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1572M301 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
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