參數(shù)資料
型號: ICS1526GLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/11頁
文件大小: 0K
描述: IC VIDEO CLK SYNTHESIZER 16TSSOP
標(biāo)準(zhǔn)包裝: 96
類型: 時鐘/頻率合成器,頻率時序發(fā)生器
PLL: 帶旁路
輸入: LVTTL
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 110MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
其它名稱: 1526GLF
800-2352-5
ICS1526GLF-ND
MDS 1526 P
Revision 051310
IDT reserves the right to make changes in the preliminary device data
identified in this publication without notice. IDT advises its customers
to obtain the latest version of all device data to verify that information
being relied upon is current and accurate.
Integrated Device Technology, Inc.
ICS1526
Video Clock Synthesizer
Features
Lead-free packaging (Pb-free)
Low jitter (typical 27 ps short term jitter)
Wide input frequency range
8 kHz to 100 MHz
LVCMOS single-ended clock outputs
Up to 110 MHz
Uses 3.3 V power supply
5 Volt tolerant Inputs (HSYNC, VSYNC)
Coast (ignore HSYNC) capability via VSYNC pin
Industry standard I2C-bus programming interface
PLL Lock detection via I2C or LOCK output pin
16-pin TSSOP package
Applications
Frequency synthesis
LCD monitors, video projectors and plasma displays
Genlocking multiple video subsystems
Pin Configuration (16-pin TSSOP)
VDDD
1
VSSD
SDA
SCL
VSYNC
I2CADR
VDDA
VSSQ
VDDQ
CLK
HSYNC_out
LOCK
VSYNC_out
OSC
HSYNC
VSSA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
General Description
The ICS1526 is a low-cost, high-performance
frequency generator. It is suited to general purpose
phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using IDT’s advanced low-voltage
CMOS mixed-mode technology, the ICS1526 is an
effective clock synthesizer that supports video
projectors and displays at resolutions from VGA to
beyond XGA.
The ICS1526 offers single-ended clock outputs to 110
MHz. The HSYNC_out, and VSYNC_out pins provide
the regenerated versions of the HSYNC and VSYNC
inputs synchronous to the CLK output.
The advanced PLL uses its internal programmable
feedback divider. The device is programmed by a
standard I2C-bus serial interface and is available in
a TSSOP16 package.
ICS1526 Functional Diagram
HSYNC
VSYNC
I2C
HSYNC_out
VSYNC_out
CLK
OSC
LOCK
ICS1526
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