- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67684 > ICS1524AM (INTEGRATED DEVICE TECHNOLOGY INC) 250 MHz, OTHER CLOCK GENERATOR, PDSO24 PDF資料下載
參數(shù)資料
| 型號： | ICS1524AM |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 250 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封裝： | 0.300INCH, SOIC-24 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 354K |
| 代理商： | ICS1524AM |
ICS1524A
16
ICS1524A Rev D 12/23/2005
PECL Outputs
For information on using the ICS1524A’s PECL output pins, please refer to Application Note 4: Designing a Custom
PECL Interface for the ICS1523
SSTL_3 Outputs
Unterminated Outputs
In the ICS1524A, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular
pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically
700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of
significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor
determining high-frequency performance of these single-ended outputs. Typically, no termination is required either for
the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz.
Terminated Outputs
SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance.
Use of transmission line techniques enables use of longer traces between source and driver without increasing
ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet
LVTTL VIH and VOL requirements, the intrinsic rise and fall times of ICS1524A SSTL outputs are only slightly improved
by termination in a low impedance.
The ICS1524A SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 Ohms
reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.
For more information on using the ICS1524A’s SSTL output pins, please refer to Application Note 3: Using SSTL_3
Outputs with CMOS or LVTTL Inputs
ICS1524A
VDD
SSTL-3 Output
330
150
Single
LVTTL
Load
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1524AMT | 250 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS1527G-60LFTR | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS1562BM-001LF | 260 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS1567M-XXX-LF | 180 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS1574BM | 130 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1524AMLF | 功能描述:IC CLK GEN SSTL_3/PECL 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1524AMLFT | 功能描述:IC CLK GEN SSTL_3/PECL 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1524AMT | 功能描述:IC CLK GEN SSTL_3/PECL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1524M | 制造商:ICS 制造商全稱:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| ICS1524MT | 制造商:ICS 制造商全稱:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復。