參數(shù)資料
型號(hào): ICS1522MLF
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 230 MHz, VIDEO CLOCK GENERATOR, PDSO24
封裝: SOIC-24
文件頁(yè)數(shù): 8/13頁(yè)
文件大?。?/td> 2240K
代理商: ICS1522MLF
4
ICS1522
Power-On Initialization
The ICS1522 has an internal power-on reset circuit that
sets the frequency of the CLK+and CLK- outputs to be half
the crystal or reference frequency assuming that they are
between 10 MHz and 25 MHz (refer to default settings in
Register Definition). Because the power-on reset circuit is
on the VDD supply, and because that supply is filtered,
care must be taken to allow the reset to de-assert before
programming. A safe guideline is to allow 20 microseconds
after the VDD supply reaches four volts.
Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1522 supports
this through a register programmable mode, AUXEN. When
this mode is set, AUXCLK will directly control the logic
levels of the CLK+ and CLK- pins while OMUX1, OMUX2,
OMUX3, and OMUX4 will control OUT1, OUT2, OUT3
and OUT4, respectively.
Power Supplies and Decoupling
The ICS1522 has three VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). These pins should
connect to the ground plane of the video board as close to
the package as is possible.
The ICS1522 has a VDDO pin which is the supply of +5
volt power to all output drivers. This pin should be connected
to the power plane (or bus) using standard high-frequency
decoupling practice. That is, capacitors should have low
series inductance and be mounted close to the ICS1522.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We
recommend that RC decoupling or zener regulation be
provided for this pin (as shown in the recommended
application circuitry). This will allow the PLL to “track”
through power supply fluctuations without visible effects.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
IPUMP
OUT
Charge Pump output (External loop filter applications)
2
SDATA
IN/OUT
Serial Data Input/Output
3
SCLK
IN
Serial Clock Input
4
SELn
IN
Serial Port enable (active Low)
5
AVDD
PWR
Analog +5 Volt Supply
6
XTAL1/EXTREF
IN
External Reference Input / Xtal Oscillator Input
7
XTAL2
OUT
Xtal Oscillator Output
8
FINE
IN
Fine Phase Adjust Input
9
VSS
PWR
Ground
10
VSS
PWR
Ground
11
OUT4
OUT
Output 4
12
OUT3
OUT
Output 3
13
VDDO
PWR
Output Driver +5 Volt Supply
14
OUT2
OUT
Output 2
15
OUT1
OUT
Output 1
16
VSS
PWR
Ground
17
IPRG
IN
Output Driver Current Programming Input
18
CLK-
OUT
Differential CLK - Output
19
CLK+
OUT
Differential CLK + Output
20
VDD
PWR
Digital +5 Volt Supply
21
PDEN
IN
Phase Detector Enable (Active High)
22
EXTFBK
IN
External Feedback Input
23
EXTVCO
IN
External VCO input
24
VVCO
IN
VCO Control Voltage Input (External loop filter applications)
Pin Discriptions
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