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參數(shù)資料
| 型號： | ICM320T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 Megapixel QXGA Digital Color CMOS Image Sensor |
| 中文描述： | 320萬像素QXGA的數(shù)字彩色CMOS圖像傳感器 |
| 文件頁數(shù)： | 27/30頁 |
| 文件大小： | 1410K |
| 代理商： | ICM320T |
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IC M320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
C opyright 2005, IC Media C orporation
http://www.ic-media.com/
3/14/2005
Page
27
1/16-Rate Subsampling Mode LineTiming
For the default 1/16-rate (512x384) line timing, a line starts when the HSYNC signal is de-asserted. The
HSYNC signal will be low for 16 PCLK clock cycles. After 25 PCLK clock cycles, DOUT [9:0] will
output three cycles of dummy pixel data, followed by 512 cycles of image data and another three dummy
pixel data. Seven clock cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure
13.
Figure 13. Default 1/16-Rate Line Timing for 570 PCLKs
1/16-Rate Subsampling Mode Frame Timing
For the default 1/16-rate (512x384) frame timing, the timing unit for the frame is derived from one line-
time unit, which is 550 PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The
VSYNC signal will be low for three line-time units. Four line-time units from the start of the frame, DOUT
[9:0] will output three lines of dummy pixel data followed by 384 lines of image data and another three
lines of dummy pixel data. Eleven (11) clock cycles later, the VSYNC signal will be de-asserted again to
start a new frame. See Figure 14.
Figure 14. Default 1/16-Rate Frame Timing - Change Registers 0x14/0x15 to 0x0010 (H)
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| ICM-324-1-GT | 功能描述:IC 與器件插座 24P / .300" MACHINED PINS RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點數(shù)量:2011 觸點電鍍:Gold 安裝風格:SMD/SMT 端接類型:Solder 插座/封裝類型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
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