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參數(shù)資料
| 型號： | ICM320T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 Megapixel QXGA Digital Color CMOS Image Sensor |
| 中文描述： | 320萬像素QXGA的數(shù)字彩色CMOS圖像傳感器 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 1410K |
| 代理商： | ICM320T |
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IC M320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
C opyright 2005, IC Media C orporation
http://www.ic-media.com/
3/14/2005
Page
19
Table 2. SIF Registers Descriptions
(continued)
Bit Description
Default
Affected by
Latent
Register
Frame
Boundary
Update
0x86 FLASH END POSITION (LSB)
0x87 FLASH END POSITION (MSB)
[15:0] Flash end position in terms of rows
0x071C
(1820)
N
Y
0x88 through 0x9C
Reserved.
0x9D MAXIMUM EXPOSURE TIME INCREASE (LSB)
0x9E MAXIMUM EXPOSURE TIME INCREASE (MSB)
[15:0] Maximum step size for exposure time increase.
0x9F through 0xB3
Reserved
0xB4 PLL CONFIGURATION (LSB)
0xB5 PLL CONFIGURATION (MSB)
PLL pre-divider (M), multiplier (N) and post-divider (R)
settings for generation of the on-chip ADC clock (ADCLK)
based on the input clock (CLKIN) frequency. The M, N and R
settings must be such that the ADC clock is 2x the frequency
of the desired output PCLK. The following equation is used to
derive the ADCLK based on a given CLKIN and M, N and R
settings:
ADCLK = N x CLKIN / (M x R)
[11:10]: PLL post divider (R)
[9:8] : PLL pre-divider (M)
[5:0] PLL multiplier (N)
PLL N, R and M Settings
[5:0]
[11:10]
0x0
N = 1
0x0
R = 1 (D)
0x1
N = 2 (D)
0x1
R = 2
0x2
N = 3
0x2
R = 3
0x3
N = 4
0x3
R = 4
0x4
N = 8
0x5
N = 16
0xB6 through 0xFF
Reserved
0x0618
(1560)
Y
Y
[9:8]
M = 1 (D)
M = 2
M = 3
M = 4
0x0
0x1
0x2
0x3
0x0001
(1)
N
Y
* Reserved bits must
not
be changed
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