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參數(shù)資料
| 型號： | ICL7104-14CPL |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter |
| 中文描述： | 1-CH 14-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ICL7104-14CPL |
5-18
Buffer Gain
At the end of the auto-zero interval, the instantaneous noise
voltage on the auto-zero capacitor is stored, and subtracts
from the input voltage while adding to the reference voltage
during the next cycle. The result is that this noise voltage
effectively is somewhat greater than the input noise voltage
of the buffer itself during integration. By introducing some
voltage gain into the buffer, the effect of the auto-zero noise
(referred to the input) can be reduced to the level of the
inherent buffer noise. This generally occurs with a buffer gain
of between 3 and 10. Further increase in buffer gain merely
increases the total offset to be handled by the auto-zero
loop, and reduces the available buffer and integrator swings,
without improving the noise performance of the system. The
circuit
recommended
for
ICL8068/ICL7104 is shown in Figure 7. With careful layout,
the circuit shown can achieve effective input noise voltages
doing
this
with
the
on the order of 1 to 2
μ
V, allowing full 16-bit use with full scale
inputs of a low as 150mV. Note that at this level, thermoelec-
tric EMFs between PC boards, IC pins, etc., due to local
temperature changes can be very troublesome. For further
discussion, see Application Note AN030.
ICL8052 vs ICL8068
The ICL8052 offers significantly lower input leakage currents
than the ICL8068, and may be found preferable in systems
with high input impedances. However, the ICL8068 has
substantially lower noise voltage, and for systems where
system noise is a limiting factor, particularly in low signal
level conditions, will give better performance.
TABLE 3. THREE-STATE BYTE FORMATS AND ENABLE PINS
CE/LD
HBEN
MBEN
LBEN
ICL7104-16
POL
O/R
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
HBEN
LBEN
ICL7104-14
POL
O/R
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
TABLE 4. TYPICAL COMPONENT VALUES
(V++ = +15V, V+ = 5V, V- = 5V, V- = -15V, f
CLOCK
= 200kHz)
ICL8052/8068 WITH
ICL7104-16
ICL7104-14
UNIT
Full scale V
IN
Buffer Gain
200
800
4000
100
4000
mV
10
1
1
10
1
V/V
R
INT
C
INT
C
AZ
C
REF
V
REF
Resolution
100
43
200
47
180
k
0.33
0.33
0.33
0.1
0.1
μ
F
1
1
1
1
1
μ
F
10
1
1
10
1
μ
F
100
400
2000
50
2000
mV
3.1
12
61
6.1
244
μ
V
FIGURE 7. ADDING BUFFER GAIN TO ICL8068
A2
+
-
A3
+
-
INTEG.
COMP.
A1
+
-
BUFFER
14
11
9
INT OUT
-INT IN
BUF OUT
10
-
BUF IN
-1.2V
2
-15V
+5V
R
INT
C
INT
1
-15V
7
8
+15V
12
+INT IN
13
8068
INT.
REF.
6
3
+BUF IN
5
REF
OUT
5k
10k
300pF
COMP
OUT
100k
10-50K
TO ICL7104
ICL8052/ICL7104, ICL8068/ICL7104
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