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參數(shù)資料
| 型號： | ICL7104-14CPL |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter |
| 中文描述： | 1-CH 14-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ICL7104-14CPL |
5-15
TABLE 1. DIRECT MODE TIMING REQUIREMENTS
(Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
t
BEA
XBEN (Min) Pulse Width.
-
300
-
ns
t
DAB
Data Access Time from XBEN.
-
300
-
ns
t
DHB
Data Hold Time from XBEN.
-
200
-
ns
t
CEA
CE/LD Min. Pulse Width.
-
350
-
ns
t
DAC
Data Access Time from CE/LD.
-
350
-
ns
t
DHC
Data Hold Time from CE/LD.
-
280
-
ns
t
CWH
CLOCK 1 High Time.
-
1000
-
ns
TABLE 2. HANDSHAKE TIMING REQUIREMENTS
(Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
t
MW
Mode Pulse (Min).
-
20
-
ns
t
SM
Mode Pin Set-Up Time.
-
-150
-
ns
t
ME
Mode Pin High to Low Z CE/LD High Delay.
-
200
-
ns
t
MB
Mode Pin High to XBEN Low Z (High) Delay.
-
200
-
ns
t
CEL
Clock 1 High to CE/LD Low Delay.
-
700
-
ns
t
CEH
Clock 1 High to CE/LD High Delay.
-
600
-
ns
t
CBL
Clock 1 High to XBEN Low Delay.
-
900
-
ns
t
CBH
Clock 1 High to XBEN High Delay.
-
700
-
ns
t
CDH
Clock 1 High to Data Enabled Delay.
-
1100
-
ns
t
CDL
Clock 1 Low to Data Disabled Delay.
-
1100
-
ns
t
SS
Send ENABLE Set-Up Time.
-
-350
-
ns
t
CBZ
Clock 1 High to XBEN Disabled Delay.
-
2000
-
ns
t
CEZ
Clock 1 High to CE/LD Disabled Delay.
-
2000
-
ns
t
CWH
Clock 1 High Time.
1250
1000
-
ns
ICL8052/ICL7104, ICL8068/ICL7104
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